Method and device for performing an approximate arithmetical division

ABSTRACT

A method and an arrangement for performing an approximate division of a constant number by a variable number in binary form. The variable number is presumed to consist of a character bit and a plurality of bits which state the absolute value of the number. The number is converted by first forming a digital word, by substituting with logic zeroes any logic ones that have a lower significance than the most significant logic one of the bits. There is then formed a new number in binary form, by reading the character bit of the variable number as a character bit and by reading the bits in the digital word in a reversed order. The arrangement may mainly comprise a single gate network.

FIELD OF THE INVENTION

The present invention relates to a method of updating an adaptivedigital filter performing an approximate arithmetical division of aconstant number by a variable number in binary form. The value of thevariable number represents the signal energy of an input signal to thefilter and exist in the form of electric signals which represent logicones and logic zeroes. The variable number includes a character bit, N1whole-number bits and N2 binary fraction bits, where N1≧0 and N2≧0.

The present invention also relates to an adaptive digital for performingan approximate division of a constant variable number by a number inbinary form. The variable number includes a character bit, N1whole-number bits and N2 binary fraction bits, where N1≧0 and N2≧0. Afirst input is used for obtaining character bit. N1+N2 inputs are usedfor obtaining the whole-number bits and binary fraction bits. A firstoutput is used for handling a a character bit. N1+N2 outputs are usedfor handling whole-number bits and binary fraction bits.

BACKGROUND OF THE INVENTION

When updating an adaptive digital filter in accordance, for instance,with the LMS-algorithm (Least Mean Square), there is calculated aconvergence factor which defines the step size. In order for the filterto function in the manner desired for different input signals, the stepsize must be inversely proportional to the signal energy of the filterinput signal. When calculating this convergence factor there istherefore a need to divide a constant number by a variable number wholevalue represents the signal energy. Division operations, however, areoften relatively demanding processes and thereby also relatively timeconsuming.

For instance, an aritmethical division operation according to one knownmethod is performed as a series of repeated so-called, conditionalsubtractions. The absolute accuracy obtained is proportional to thenumber of iterations. Arithmethical division operations can also beperformed with the aid of equipment that has a relatively large memorycapacity. One example in this regard is found described in U.S. Pat. No.4,707,798, according to which an approximate arithmethical division iseffected by table look-up in a memory in combination with interpolation.

SUMMARY OF THE INVENTION

One object of the present invention is to provide a method which willenable an arithmetical division of the kind mentioned in the backgroundto be carried out rapidly and with the aid of simple equipment. This isachieved in two stages. There is first formed a digital word, bysubstituting with logic zeroes any logic ones which have a lowersignificance than the most significant logic one of the bits which givethe absolute value of the variable number. There is then formed inbinary form a new number which has similar character bits to thevariable number, and the bits in the digital word are read in thereverse sequence.

Although the division achieved when practicing the method is not exact,it is, however, sufficiently exact for calculating the convergencefactor when updating adaptive filters. For instance, it will be obviousthat a high signal energy will give rise to a low convergence factor,and vice versa.

Another object of the invention is to provide an arrangement of theaforesaid kind of simple construction which will enable an approximatedivision to be carried out rapidly. The device comprises essentiallyonly one logic device which functions to substitute with logic zeroesany logic ones that have a lower significance than the most significantlogic one.

BRIEF DESCRIPTION OF THE DRAWINGS

The invention will now be described in more detail with reference to theaccompanying drawings, in which:

FIGS. 1 and 2 are tables illustrating examples of the relationshipbetween mutually different input values and output values in binary formwhen performing an inventive division operation, and also differentdigital words which are constructed as a link in such a division; and

FIG. 3 illustrates a gate network which constitutes an example of anapparatus for carrying out an inventive division operation.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS OF THE INVENTION

In FIG. 1, the column furthest to the left in the table shows examplesof different numbers in binary form whose values vary between zero and15/16. The first bit in each number is a character bit and has zerovalue, which in the case of the illustrated example signifies that thenumber is positive. The point following the first zero is a so-calledbinary point and indicates that the subsequent bits have the values 1/2,1/4, 1/8 and 1/16, as will also be seen from FIG. 1. Thus, theillustrated binary numbers do not include a whole-number bit, butinclude solely one character bit and four so-called binary fractionbits.

When effecting arithmetical division in accordance with the invention,corresponding to an approximative division of a constant number by oneof the binary numbers in the left-hand column, a digital word is formedfrom the binary fraction bits in a first stage of the process, i.e. fromthe four bits to the right of the character bit in the binary number.Different digital words of this kind are shown in the centre column ofthe FIG. 1. Each of these words is formed by substituting with logiczeroes any logic ones which have a lower significance than the mostsignificant logic one in the binary number. Each such digital word willthus consist of a single logic one and three logic zeroes, with theexception of the lowermost word in the table, which corresponds to thebinary number zero and which consists of four logic zeroes.

A new number is formed in binary form in a second stage, and theright-hand column of FIG. 1 illustrates the different number thusformed. Each of the new numbers has a character bit similar tocorresponding numbers in the left-hand column, and the binary point islocated in the same position as in the corresponding number. The binarybits which follow the binary point coincides with the bits incorresponding digital words in the centre column, but are read in thereverse order.

It will be seen from the table, that the number 1/16 is converted to thenumber 1/2, the numbers 1/8 and 3/16 are converted to the number 1/4,the numbers 1/4-7/16 are converted to 1/8, the numbers 1/2-15/16 areconverted to the number 1/16 and the number zero remains zero. Thus,with the exception of the number zero, a number of relatively high valueresults in a number of relatively low value, and vice versa. Accordingto the described method, attention is paid solely to the mostsignificant logic one of the variable number, and consequently several,mutually different input values can result in one and the same outputvalue. Nevertheless, the method can be seen as an approximate divisionof a constant number by the variable number. In the case of those binarynumbers which have only one single logic one, i.e. the numbers 1/16,1/8, 1/4, and 1/2, the method provides an exact division between theconstant number 1/32 and the number concerned. For instance, the number1/16 which in binary form is written as 0.0001 is converted to 0.1000,which is equal to 1/2. The number 15/16 which in binary form is writtenas 0.111 is, however, converted to 1/16. If this division is tocorrespond to a division with 15/16, the numerator will therewith be15/(16×16) =30/(16×32), i.e. almost 2×1/32. This numerator is thusalmost twice as large as the numerator calculated in the aforegoing,i.e. when considering binary numbers which contain only a single logicone. Thus, for all binary numbers in the table, with the exeption of thenumber zero, the division method can be said to correspond to anapproximate division of a constant number whose value lies approximatelyin the middle of 1/32 and 2/32 and the binary number concerned.

In the aforegoing it has been assumed throughout that the binary numbersare positive. In that instance when the numbers are presented incharacter-value representation, the division method would alsocorrespond to an approximate division of negative numbers. With suchrepresentation, a positive and an equally large negative number woulddiffer solely with respect to the character bits. This does not apply,however, in two complement representation.

Since division with zero is not a defined operation, the division of thenumber zero can, in principle, be arbitrarily selected. In the presentcase, it has been considered appropriate for the number zero to resultin the number zero subsequent to division. This is because when thedivision process is applied in conjunction with adjustment to thesettings of adaptive filters, it is probable that the number zero on theconverter input originates from a momentarily "silent" transmissionchannel. This shall not result in an adjustment or change to the filtersetting.

FIG. 2 illustrates a second table that contains various numbers inbinary form. These numbers coincide with the numbers in the table ofFIG. 1, but with the binary point having been moved two places to theright. The numbers therefore have two whole-number bits having thevalues 2 and 1, and two binary fraction bits having the values 1/2 and1/4, which are marked in FIG. 2. The numbers are converted according tothe same principle as that applied with the numbers shown in FIG. 1, andthe digital words in the centre column therefore coincide exactly withcorresponding words in FIG. 1. In this case, the converted numbers inthe right-hand column include two binary bits to the right of the binarypoint, i.e. two binary fraction bits.

In this case, the arithmetic division of binary numbers which havesolely a single logic one corresponds to the division of 1/2 by thenumber concerned. For instance, 1/4 is converted to 2. The number 33/4is written in binary form as 011.11 and is converted to 1/4. Thiscorresponds to a division of the number (30/16)×1/2, i.e. almost 2×1/2,by the number 33/4. In the case of the binary numbers shown in the tableof FIG. 2, the division method will thus correspond to an approximatedivision of a constant number whose value lies roughly centrally between1/2 and 1, and the binary number concerned. As in the earlier case, thenumber zero is an exception, since this number is not changed at all.

FIG. 3 illustrates an exemplifying embodiment of an arrangement forcarrying out an approximate division in accordance with the aforegoing.The arrangement has five inputs 10-14 and five outputs 50-54. The input10 is connected to the output 50 and is intended to be supplied with thecharacter bit of a binary input number. The character bit is thustransmitted unchanged from the input 10 to the output 50. The mostsignificant bit, the next most significant bit and so on of the inputnumber are applied to the inputs 11-14 in that sequence. The inputs11-14 are connected to a logic device 20 having outputs 21-24. The logicdevice 20 will be described in more detail hereinafter, and functions tofind the most significant logic one on the inputs 11-14 and tosubstitute with logic zeroes any logic ones of lower significance. Thedigital words shown in the centre columns in FIGS. 1 and 2 are thushandled on the outputs 21-24.

The outputs 21-24 from the device 20 are connected to the outputs 51-54of said device, by coupling the output 21 to the output 54, the output22 to the output 53, and so on. In this way, the bits in the digitalword from the device 20 will occur in a reversed order on the outputs51-54 of said device. The character bit on the output 50 and the bits onthe output 51-54 thus form the binary words shown in the respectiveright-hand columns of FIGS. 1 and 2.

In the case of the illustrated example the device 20 comprises a gatenetwork which includes four AND-gates 31-34 and two OR-gates 41-42 andis intended to convert binary numbers which have four binary bits inaddition to the character bits. An input 15 and an output 25 areintended for so-called carry bits which are used when several gatenetworks of the illustrated kind are connected in cascade. This makes itpossible to convert binary numbers comprising more than four bits. Ifthe gate network is not cascade-connected to a similar network for bitsof higher significance than the bit on the input 11, a logic zero issent to the carry input 15.

A logic zero on the carry input 15 will hold the gate 31 open for apossible logic one on the input 11 for the most significant bit in abinary number supplied to the network. If the most significant bit is alogic one, a logic one will therefore also appear on the output 21 ofthe gate 31. The presence of a logic one on the input 11 will alsoresult in the presence of a logic zero on a negated output of the gate41, and this logic zero will latch the gates 32-34 so that logic zeroesoccur on the outputs 22-24 irrespective of whether logic ones or logiczeroes appear on the inputs 12-14. If the most significant bit is,instead, a logic zero, a logic zero will also appear on the output 21and a logic one will appear on the output of the gate 41. This logic oneholds the gate 32 open for a possible logic one on the input 12 for thenext most significant bit of the binary number. A logic one on the input12 will, at the same time, latch the gates 33 and 34, so that logiczeroes will appear on the outputs 23 and 24.

If the most significant logic one of the number appears on the input 13,a logic one will appear on the output 23 and the gate 34 will be heldlatched. A logic one will appear on the output 24 only if logic zeroesappear on the inputs 11-13 at the same time as a logic one appears onthe input 14.

If a logic one appears on at least one of the inputs 11-14, a logic onewill appear on the carry-output 25. When a logic one appears on thecarry-input 15, the gates 31-34 are latched, which causes logic zeroesto appear on all outputs 21-24, and also on the carry output 25.

As will be understood, the logic ones and logic zeroes recited in thedescription above are, in practice, different electrical signals whichrepresent such logic values.

While a particular embodiment of the present invention has beendescribed and illustrated, it should be understood that the invention isnot limited thereto since modifications may be made by persons skilledin the art. The present application contemplates any and allmodifications that fall within the spirit and scope of the underlyinginvention disclosed and claimed herein.

We claim:
 1. A system for performing an approximate arithmeticaldivision of a constant number by a number in binary form which includesa character bit, N1 whole-number bits and N2 binary character bits,where N1≧0 and N2≧0, including a first input signal terminal forobtaining said character bit, N1+N2 input signal terminals for obtainingsaid whole-number bits and binary character bits, a first outputterminal for handling a character bit and N1+N2 output terminals forhandling whole-number bits and binary character bits, comprising:a logicdevice connected to said N1+N2 input terminals and said N1+N2 outputterminals having means for receiving a first digital word from saidinput terminals, means for generating a second digital word whichcoincides with the first digital word, and means for substituting anylogic ones of said second word which are less significant than the mostsignificant logic one with logic zeroes; wherein said first outputterminal is connected to said first input terminal and said N1+N2 outputterminals are connected to corresponding output terminals of said logicdevice; and wherein starting with connecting the least significant bitof said second digital word to the most significant bit of said wholenumber and binary fraction bits, said logic device sequentially andrepetitively connects the least significant bits of said second digitalword to the most significant bits of the whole-number and binaryfunction bits.
 2. An arithmetic apparatus for performing an approximatearithmetical division of a first constant number by a number in binaryform while includes a character bit, N1 whole-number bits and N2 binarycharacter bits, where N1≧0 and N2≧0, comprising:first input means forreceiving a first character bit value; N1+N2 input means for receivingN1 whole-number bit values and N2 binary character bit values; a logicmeans, connected to said N1+N2 input means, for transforming a first setof logic bit values received from said N1+N2 input means into a secondset of logical bit values by replacing logic one values less significantthan a most significant logic one value in said first set of values withlogic zero values; first output means, connected to said first inputmeans, for generating said first character bit values; and second outputmeans, connected to said logic means, for receiving said second set oflogical bit values and generating a third set of logical bit valuescorresponding to said second set of logical bit values in reverse order.3. The arithmetic apparatus according to claim 2, wherein said N1+N2output bit values represent a quotient of a dividend, corresponding tosaid constant number, and a divisor, corresponding to said variablenumber.